The present invention relates to a silicon carbide semiconductor device, having J-FETs, and a manufacturing method.
Such a silicon carbide semiconductor device, having J-FETs, is provided in, for example, an unexamined patent publication H2000-312008. A cross-sectional view of an n-channel J-FET, provided in this publication, is shown in FIG. 33. As shown in this figure, the n-channel J-FET is formed using a substrate consisting of an n−-type drift layer J2 grown on an n+-type substrate J1, which consists of SiC. A p-type first gate area J3 is formed on the surface of the n−-type epi-layer J2. A trench J4, penetrating the first gate area J3 and reaching the n−-type drift layer J2, is then formed.
An n−-type channel layer J5 is grown epitaxially on a surface of the first gate area J3 as well inside the trench J4. A p-type second gate area J6 is then formed on a surface of the n−-type channel layer J5 inside the trench J4. Furthermore, n+-type source areas J7 are formed in the n−-type channel layer J5 at areas that are not located between the first and second gate areas J3 and J6.
Furthermore, source electrodes J9, which are electrically connected to the n+-type source areas J7, and a gate electrode J8, which is electrically connected to the first and second gate areas J3, J6, are provided. Finally, a drain electrode J10 is provided on a backside of the n+-type substrate J1 to complete the J-FET shown in FIG. 22.
In this J-FET, a voltage being applied to the gate electrode J8 is controlled for controlling the distance over which a depletion layer extends through the n−-type channel layer J5 and for forming a channel, so that current flows between the sources and the drain through the channel.
In the J-FET described above, the n−-type channel layer J5 is grown epitaxially inside the trench J4. Say that a bottom surface of the trench J4 is surface a, and side walls are surfaces c. The rates of epitaxial growth differ between the surface a and the surfaces c, and the quality of the n−-type channel layer J5 would be different between the film formed on the bottom surface of the trench J4 and on the side walls. More specifically, the amounts of impurity doping in the n−-type channel layer J5 can vary by an order magnitude between different areas.
Although epitaxial growth is less susceptible to crystal defects compared with ion implanting, crystal defects, nevertheless, are created because the epitaxial growth takes place inside the trench J4.
When the n−-type channel layer J5, which is used as a channel, has inconsistent levels of impurity doping and has crystal defects, electrical characteristics of the currents flowing through the channel can be inconsistent. Therefore, it is difficult to form J-FET devices with uniform quality levels.
As provided in the unexamined patent publication H9-172187 and 2000-31483, a silicon carbide semiconductor device that addresses this problem may be formed by using the drift layer as the channel area to ensure uniform quality.
A silicon carbide semiconductor device provided in the unexamined patent publication H9-172187 is shown in FIG. 34. The reference numerals in FIG. 33 are used again in FIG. 34 for the like parts. In this semiconductor device, a multitude of trenches J4 are formed at the surface of the n−-type drift layer J2, and a p-type epitaxial film J11 is formed on inner side walls of the trenches J4. An n-type source area J12 is formed on the surface of the drift layer J2, excluding the areas where the trenches J4 are formed. The channel area J13 is an area beneath this source area J12. In this semiconductor device, the channel area J13 is located between pn junctions found between the channel area J13 and the epitaxial film J11.
The n−-type drift layer J2 is formed by an epitaxial growth method, and the drift layer J2 is used as the channel area J13 in the structure described above. For this reason, uniform quality is ensured with this J-FET.
In J-FET devices used in automotive applications, currents flowing through the source and the drain should be turned off when a bias on the gate is turned off, or the device should have a normally-off characteristic. Such a normally-off characteristic is obtained if depletion layers extend into the channel area from the pn junctions between the channel area J13 and the p-type epitaxial film J11 and pinch off the channel area when a bias is not applied to the gate. Therefore, the smaller the width of the channel area, the easier it is for the depletion layers from both sides of the channel area to reach one another and pinch off the channel area.
In the silicon carbide semiconductor device shown in FIG. 34, however, the width of the channel is determined by the distance between the adjacent trenches at the surface of the drift layer J2. Therefore, the width of the channel area is determined by the width of the area left behind on the drift layer J2 after the trenches are etched.
Normally, the width of the channel area should be slightly less than one micron in order to ensure a pinch off by the depletion layers. It is difficult, however, to achieve sub-micron spacing between adjacent trenches with trench etching technology. Process non-uniformity becomes significant when trenches are etched with sub-micron spacing in between, making it difficult to obtain J-FET devices with normally-off characteristics.
A silicon carbide semiconductor device provided in the unexamined patent publication 2000-31483 is shown in FIG. 35. In this semiconductor device, a first gate area J20 is formed by ion implanting on an area where trenches J4 are not formed on a drift layer J2, or an area left behind by a trench etching process.
Gate electrodes J22 are formed on inner walls of trenches J4 on top of an insulating film J21 formed with, for example, an oxide film. In other words, MOS structures, consisting of the drift layer J2, the insulating film J21a, and the gate electrodes J22, are formed near side walls of the trenches J4. Out of the drift layer J2, areas between the first gate area J20 and the side walls of the trenches J4 become channel areas J23. Therefore, the drift layer J2 is used as the channel areas J23. For this reason, uniform quality is ensured with the J-FET devices.
Furthermore, second gate areas J24 are formed in the drift layer J2 at areas facing bottom surfaces of the trenches J4. This semiconductor device has junctions between the first gate area J20 and the insulating film J21a and junctions between the first gate area J20 and the second gate areas J24.
When a bias is not applied to the gates, depletion layers extend from pn junctions between the first gate area J20 into the channel areas J23, and depletion layers also extend out from the insulating films J21a into the channel areas J23. As a result, the channel areas J23 get pinched off.
As mentioned earlier, the widths of the channel areas J23 in this semiconductor device is adjusted by forming the first gate area J20 by ion implanting. However, when the semiconductor device, having the structure described above, is manufactured, the widths of the channel areas become non-uniform, making it difficult to ensure a normally-off characteristic with the semiconductor device.
Even if the resulting semiconductor device were to offer a normally-off characteristic, the device faces another problem. When a bias is applied to the gates, or when the device is turned on, the depletion layers that are pinching off the channel areas J23 become smaller, and currents flow between the source and the drain. Because a voltage is applied on the oxide film, the depletion layers extending from the MOS structure into the channel areas J23 do not show much change, and only the depletion layers extending from the pn junctions become smaller. In other words, only the size of the depletion layers extending from the pn junctions is controlled, and the channels remain narrow even when the device is turned on. As a result, resistance is large.
In the structures shown in FIG. 34 and FIG. 35, the source electrodes J9 and the gate electrodes J8, J22 are formed in the cell area. Contact areas are required for the source electrodes J9 and the gate electrodes J8, J22 on the surfaces of the semiconductor substrate. Furthermore, an insulating area J21b is required for isolating the source electrode J9 and the gate electrode J22, especially in the structure shown in FIG. 24, in which the source electrode J9 and the gate electrode J22 are formed adjacently.
Furthermore, because the trenches J4 are formed on the surface of the semiconductor substrate in the structures shown in FIG. 34 and FIG. 35, steps are formed at the surface. For this reason, it is difficult to ensure good wire bonding characteristics, when wires are bonded on these devices for external contacts. The gate electrode J22 is especially susceptible to open failures at the steps J25 in the structure shown in FIG. 35.